Pipeline Registers Vulnerability Framework Oriented on Instruction Set Architecture Reliability Analysis

Hdl Handle:
http://hdl.handle.net/11285/619516
Title:
Pipeline Registers Vulnerability Framework Oriented on Instruction Set Architecture Reliability Analysis
Authors:
Flores Estrada, Roberto A.
Issue Date:
02/09/2016
Abstract:
Technology Scaling continues evolving in smaller transistor feature sizes and more dense integrated circuits. The goal is to achieve improvements on speed, power consumption, and cost. However, as supply voltage decreases and switching speed increases, the Soft Error Rate increases. A Soft Error is an intermittent fault caused by cosmic rays, alpha particles in material packaging, crosstalk, etc. and it may produce a sequential element to flip the value of its stored contents. Reliability is a major concern, especially when developing embedded systems, and as SER increases the system designers will have to develop systems that are reliable even when their components are no longer dependable. We developed a dual abstraction level framework, which can identify the vulnerable bits of the pipeline registers per instruction of a RTL model. These bits then are used at a performance level simulator to calculate statistical reliability data of executed programs based on the vulnerability context of the RTL model. As implementation example we used our methodology on AMBER 2 ARMv2a OpenCores RTL core as target. We provided analysis of the instructions vulnerability and calculated both the pipeline registers vulnerability factor of several MiBench Benchmarks and the vulnerability rate of simple sum of arrays test program. Additionally, we presented an initial view of a new estimation approach for the conditional execution vulnerability for ARM ISA. The approach can be used dynamically for vulnerability quantification or statically for protection.
Keywords:
Technology Scaling; Vulnerability; Pipelines; RTL Model; Architecture Reliablity
Degree Program:
Maestría en Ciencias en Ingeniería Electrónica con Especialidad en Sistemas Electrónicos
Advisors:
Dr. Alfonso Avila Ortega
Committee Member / Sinodal:
Dr. José Isabel Gómez Quiñones; Dr. Luis Ricardo Salgado Garza; Dr. Graciano Dieck Assad; Dr. Reiley Jeyapaul
Degree Level:
Maestro en Ciencias en Ingeniería Eléctrica con Especialidad en Sistemas Electrónicos
School:
Escuela de Ingeniería y Ciencias
Campus Program:
Campus Monterrey
Discipline:
Ingeniería y Ciencias Aplicadas / Engineering & Applied Sciences
Appears in Collections:
Ciencias Exactas

Full metadata record

DC FieldValue Language
dc.contributor.advisorDr. Alfonso Avila Ortegaes
dc.contributor.authorFlores Estrada, Roberto A.en
dc.date2013-12en
dc.date.accessioned2016-09-02T11:08:01Z-
dc.date.available2016-09-02T11:08:01Z-
dc.date.issued02/09/2016-
dc.identifier.urihttp://hdl.handle.net/11285/619516-
dc.description.abstractTechnology Scaling continues evolving in smaller transistor feature sizes and more dense integrated circuits. The goal is to achieve improvements on speed, power consumption, and cost. However, as supply voltage decreases and switching speed increases, the Soft Error Rate increases. A Soft Error is an intermittent fault caused by cosmic rays, alpha particles in material packaging, crosstalk, etc. and it may produce a sequential element to flip the value of its stored contents. Reliability is a major concern, especially when developing embedded systems, and as SER increases the system designers will have to develop systems that are reliable even when their components are no longer dependable. We developed a dual abstraction level framework, which can identify the vulnerable bits of the pipeline registers per instruction of a RTL model. These bits then are used at a performance level simulator to calculate statistical reliability data of executed programs based on the vulnerability context of the RTL model. As implementation example we used our methodology on AMBER 2 ARMv2a OpenCores RTL core as target. We provided analysis of the instructions vulnerability and calculated both the pipeline registers vulnerability factor of several MiBench Benchmarks and the vulnerability rate of simple sum of arrays test program. Additionally, we presented an initial view of a new estimation approach for the conditional execution vulnerability for ARM ISA. The approach can be used dynamically for vulnerability quantification or statically for protection.es
dc.language.isoen-
dc.rightsOpen Accessen
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titlePipeline Registers Vulnerability Framework Oriented on Instruction Set Architecture Reliability Analysisen
dc.typeTesis de Maestríaes
thesis.degree.grantorInstituto Tecnológico y de Estudios Superiores de Monterreyes
thesis.degree.levelMaestro en Ciencias en Ingeniería Eléctrica con Especialidad en Sistemas Electrónicoses
dc.contributor.committeememberDr. José Isabel Gómez Quiñoneses
dc.contributor.committeememberDr. Luis Ricardo Salgado Garzaes
dc.contributor.committeememberDr. Graciano Dieck Assades
dc.contributor.committeememberDr. Reiley Jeyapaules
thesis.degree.disciplineEscuela de Ingeniería y Cienciases
thesis.degree.nameMaestría en Ciencias en Ingeniería Electrónica con Especialidad en Sistemas Electrónicoses
dc.subject.keywordTechnology Scalinges
dc.subject.keywordVulnerabilityes
dc.subject.keywordPipelineses
dc.subject.keywordRTL Modeles
dc.subject.keywordArchitecture Reliablityes
thesis.degree.programCampus Monterreyes
dc.subject.disciplineIngeniería y Ciencias Aplicadas / Engineering & Applied Sciencesen
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