Pipeline Registers Vulnerability Framework Oriented on Instruction Set Architecture Reliability Analysis
Flores Estrada, Roberto A.
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Technology Scaling continues evolving in smaller transistor feature sizes and more dense integrated circuits. The goal is to achieve improvements on speed, power consumption, and cost. However, as supply voltage decreases and switching speed increases, the Soft Error Rate increases. A Soft Error is an intermittent fault caused by cosmic rays, alpha particles in material packaging, crosstalk, etc. and it may produce a sequential element to flip the value of its stored contents. Reliability is a major concern, especially when developing embedded systems, and as SER increases the system designers will have to develop systems that are reliable even when their components are no longer dependable. We developed a dual abstraction level framework, which can identify the vulnerable bits of the pipeline registers per instruction of a RTL model. These bits then are used at a performance level simulator to calculate statistical reliability data of executed programs based on the vulnerability context of the RTL model. As implementation example we used our methodology on AMBER 2 ARMv2a OpenCores RTL core as target. We provided analysis of the instructions vulnerability and calculated both the pipeline registers vulnerability factor of several MiBench Benchmarks and the vulnerability rate of simple sum of arrays test program. Additionally, we presented an initial view of a new estimation approach for the conditional execution vulnerability for ARM ISA. The approach can be used dynamically for vulnerability quantification or statically for protection.